Jaeyoon Lee’s poster, “ROC-DRAM: Low Latency and Low Power DRAM using Rows with Opposite Charging”, has been accepted to Design Automation Conference (DAC23). Congratulation!
If you’re interesting in researching cutting-edge computer architecture and want to change the world, please send your CV to dale40@gmail.com The lab will support a full tuition and stipends, with chances of attending top-tier international conferences.
Jaeyoon Lee’s poster, “ROC-DRAM: Low Latency and Low Power DRAM using Rows with Opposite Charging”, has been accepted to Design Automation Conference (DAC23). Congratulation!